The present invention relates generally to the field of data transfer technology. More specifically, the present invention relates to an apparatus, method, and system for intermediate validation of data transferred between a storage device and a host.
As computer devices and systems continue to advance and become more complex, effective and efficient techniques for transferring data between various components in computer systems have become more and more critical in system design and implementation. In particular, data transfer between an I/O device (e.g., a hard disk) and a host device (e.g., system memory) has been constantly examined and improved in order to improve the system""s total performance and reliability. In the PC industry, the performance of the hard disk drive, which is the central I/O device of the PC, has become more and more important due to continual performance increases in the CPU, system memory and other various components of the PC.
The hard drive interface in a PC system provides the path for transferring data between a hard drive and system memory. The vast majority of PC systems today rely on the Advanced Technology Attachment (ATA), also referred to as the Integrated Drive Electronics (IDE), hard disk drive interface to transfer data between the hard disk and the system memory. The original ISA-dependent ATA/IDE interface was limited to a data transfer rate of about 4 Mbytes/sec to about 8 Mbytes/sec. Various data transfer protocols or standards have been developed to facilitate and control the various aspects of data transfer through an ATA/IDE interface. Data transfer protocols or standards such as the programmed input/output (PIO) and direct memory access (DMA) modes were developed to take advantage of the local bus architectures that replaced the original ISA bus. ATA interface modes have improved from PIO to DMA and now Ultra DMA, with data transfer rates up to 33.3 Mbytes/sec and 66.6 Mbytes/sec according to the Ultra ATA/33 and the Ultra ATA/66 protocols, respectively.
ATA-4 includes Ultra ATA/33 which uses both the rising and falling edges of the strobe signal as signal separators. Using both edges of the strobe signal effectively allows the available transition frequency to be doubled without increasing the frequency of the strobe, thus doubling the burst transfer rate. ATA-5 includes Ultra ATA/66 which doubles the Ultra ATA burst transfer rate by reducing setup times and increasing the strobe rate.
As mentioned before, DMA protocol allows a peripheral device (e.g., a hard drive) to directly transfer data to the system""s memory with minimal involvement from the system processor. DMA increases transfer speed by using a DMA controller or DMA engine to manage the data transfer between the device and the system memory rather than the system processor. Ultra DMA is a data transfer protocol to be used with the READ DMA, WRITE DMA commands and data transfer for PACKET commands.
A disk read request (e.g., an Ultra DMA READ command) typically contains two portions: a demand portion and a pre-fetch portion. First, the demand portion of the request is retrieved from the disk. Second, additional contiguous pre-fetch data is transferred from the disk to the system memory in the background after the transfer of the demand portion is completed. Currently, the host has to wait until the entire data transfer including the pre-fetch data is completed before it can proceed to use the demand portion of the read request. System performance is not optimized due to the current method of pre-fetching because the host cannot proceed to use the demand portion of the data transfer until the entire transfer is completed although the transfer of the demand portion will have completed long before the entire transfer is completed. Since the pre-fetched data is speculative, in order to avoid incurring a performance penalty, the host should not have to await the completion of the pre-fetch data before it can proceed to use the demand-fetched data. In addition, as the pre-fetch length is long and the CPU power continues to increase, it is increasing likely that a request for subsequent data (i.e., a pre-fetch hit) will be submitted by the host while the pre-fetch transfer is still in progress. Since most transfer lengths initiated by the host are typically small, the transfer of subsequent requested data which is a pre-fetch hit would have been completed before the entire pre-fetch request is completed. The host should not have to wait for the entire transfer to complete before allowed to proceed with the portion of the data transfer which is pre-fetch hit. Similarly, when a request is issued which is not a pre-fetch hit, the host should not have to wait for the entire pre-fetch transfer to complete before it can abort the pre-fetch request in progress and proceed with servicing the new request.
According to one aspect of the present invention, a method is provided in which a device, in response to a read request issued by a host, transfers data to the host through a series of direct memory access (DMA) data in bursts. The host is allowed to interrupt the data transfer and terminate the data in burst upon completion of a portion of the data transfer.